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Patent # Description
US-9,819,350 Digital phase locked loop for low jitter applications
A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path...
US-9,819,190 Islanding a plurality of grid tied power converters
A power system having a plurality of power converters coupled together at a point of common coupling (PCC). The power converters are coupled to a load and...
US-9,818,873 Forming stressed epitaxial layers between gates separated by different pitches
Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a...
US-9,818,688 Dielectric region in a bulk silicon substrate providing a high-Q passive resonator
Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive...
US-9,818,653 Semiconductor TSV device package to which other semiconductor device package can be later attached
A first package includes a laminate layer, an overmold layer above and in direct contact with the laminate layer, and a logic circuit-through-silicon via (TSV)...
US-9,818,650 Extra gate device for nanosheet
A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is...
US-9,818,637 Device layer transfer with a preserved handle wafer section
Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and...
US-9,818,542 Gate-all-around fin device
A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality...
US-9,818,062 Using cohorts to infer attributes for an input case in a question answering system
A cohort analysis mechanism analyzes cohorts to infer one or more additional attributes for an input case to provide a refined input case to answer a question...
US-9,817,655 Managing software assets installed in an integrated development environment
A software plugin integrated with the development environment maintains a list of independently managed assets that are installed within the development...
US-9,816,973 Industrial process stream compositional headspace analysis
A system and method for compositional analysis of a process stream in an industrial process transports a liquid process stream through an absorption/desorption...
US-9,815,254 Lightweight, high flow hose assembly and method of manufacture
A hose assembly, preferably a garden hose assembly, including a fabric jacketed tube that is lightweight, durable and versatile. The tube is radially expandable...
US-9,814,955 Adjustable sports paddle
An adjustable sports paddle including a handle that extends to a neck portion and a substantially ovular frame. The frame supports first and second striking...
US-9,814,295 Consumer products applicator and related methods
Consumer product application device and method involving a plurality of reservoirs and intelligence for selectively controlling the delivery of consumer...
US-D802,436 Supplement container with surface ornamentation
US-D802,352 Barrel evaporator
US-9,813,264 Millimeter wave phase shifters using tunable transmission lines
Tunable phase shifters and methods for using the same include a signal line; one or more grounding lines; one or more crossing lines below the signal line in...
US-9,812,447 Bipolar junction transistors with extrinsic device regions free of trench isolation
Device structures and fabrication methods for a device structure. One or more trench isolation regions are formed in a substrate to surround a device region. A...
US-9,812,359 Thru-silicon-via structures
Stress generation free thru-silicon-via structures with improved performance and reliability and methods of manufacture are provided. The method includes...
US-9,810,357 Lightweight, high flow hose assembly and method of manufacture
A hose assembly, preferably a garden hose assembly, including a fabric jacketed tube that is lightweight, durable and versatile. The tube is radially expandable...
US-9,806,723 Digital phase locked loop for low jitter applications
A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path...
US-9,806,221 Germanium photodetector with SOI doping source
Various particular embodiments include a method for forming a photodetector, including: forming a structure including a barrier layer disposed between a layer...
US-9,806,025 SOI wafers with buried dielectric layers to prevent Cu diffusion
An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor...
US-9,805,990 FDSOI voltage reference
An integrated circuit having a reference device and method of forming the same. A reference device is disclosed having: a fully depleted n-type MOSFET...
US-9,805,935 Bottom source/drain silicidation for vertical field-effect transistor (FET)
A method for manufacturing a semiconductor device includes forming a first active region on a semiconductor substrate, forming a semiconductor layer on the...
US-9,805,318 Method, system and program product for conditionally controlling changes to key data fields in a project database
A method, system and program product for performing one or more actions in response to a change made to a key data field in a project management application for...
US-9,802,844 Portable pathogen deactivation method and apparatus
A portable, non-filtering, microorganism deactivation device for treating water contaminated with harmful bacteria such as E. coli and fecal coliform, includes...
US-9,800,434 Millimeter wave phase shifters using tunable transmission lines
Tunable phase shifters and methods for using the same include a signal line; one or more grounding lines; one or more crossing lines below the signal line in...
US-9,799,720 Inductor heat dissipation in an integrated circuit
The present invention relates generally to semiconductor structures and methods of manufacturing and, more particularly, to improving heat dissipation of...
US-9,799,693 Photodetector and method of forming the photodetector on stacked trench isolation regions
Disclosed are structures and methods of forming the structures so as to have a photodetector isolated from a substrate by stacked trench isolation regions. In...
US-9,799,652 Semiconductor structure with a dopant implant region having a linearly graded conductivity level and method of...
Disclosed are methods that employ a mask with openings arranged in a pattern of elongated trenches and holes of varying widths to achieve a linearly graded...
US-9,799,618 Mixed UBM and mixed pitch on a single die
Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and...
US-9,799,554 Method for coating a substrate
A method for coating substrates provided with vias uses a first step in which the substrate is conditioned and a second step in which the substrate is coated...
US-9,799,413 Multi-domain fuse management
A fuse controller comprises: a fuse bay, a bus, an engine, and an interface. The fuse bay stores repair and setting information for a plurality of fuse domains...
US-9,799,386 STT MRAM midpoint reference cell allowing full write
Improved STT MRAM midpoint reference cell configurations are provided. In one aspect, a STT MRAM midpoint reference cell includes: a plurality of word lines...
US-9,794,126 Data compression of a sequence of binary data
Apparatus and associated methods relate to compressing a sequence of binary data by encoding difference values between adjacent data in the sequence. For each...
US-9,793,991 Optically interfaced remote data concentrator
A remote data concentrator includes a front end interface, a plurality of back end interfaces and a control circuit. The front end interface is configured to...
US-9,793,272 Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction and...
A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an...
US-9,793,271 Semiconductor device with different fin pitches
A method for forming a semiconductor device includes forming a first fin and a second fin on a substrate, the first fin arranged in parallel with the second...
US-9,792,251 Array of processor core circuits with reversible tiers
Embodiments of the invention relate to an array of processor core circuits with reversible tiers. One embodiment comprises multiple tiers of core circuits and...
US-9,792,052 Nonvolatile memory interface for metadata shadowing
A memory includes multiple non-volatile memory devices, each having multiple nonvolatile memory cells. A write controller is configured to stream bits to the...
US-9,791,771 Photomask structure with an etch stop layer that enables repairs of detected defects therein and extreme...
Disclosed are a repairable photomask structure and extreme ultraviolet (EUV) photolithography methods. The structure includes a multilayer stack, a protective...
US-9,791,507 Customer-transparent logic redundancy for improved yield
Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More...
US-9,791,502 On-chip usable life depletion meter and associated method
Disclosed is an integrated circuit (IC) chip having an on-chip usable life depletion meter. This meter incorporates programmable bits, which represent units of...
US-9,791,497 Method of characterizing and modeling leakage statistics and threshold voltage for ensemble devices
An approach for determining leakage current and threshold voltage for ensemble semiconductor devices, implemented in a computer infrastructure having computer...
US-9,791,372 Multiplexing and quantification in PCR with reduced hardware and requirements
Methods and algorithms for a multiplexed single detection channel amplification process and quantification of generated amplicons is presented. Various...
US-9,788,134 Method for processing of sound signals
A method for processing audio signals for creating a three dimensional sound environment includes: receiving at least one input signal from at least one sound...
US-9,787,531 Automatic notification of isolation
A method and associated systems of automatic notification of isolation of a first networked device. In response to detecting that it is not being properly...
US-9,786,835 Backside integration of RF filters for RF front end modules and design structure
A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a...
US-9,786,788 Vertical-transport FinFET device with variable Fin pitch
A semiconductor device includes a plurality of vertical-transport fin field effect transistors that are arranged at a locally-variable fin pitch. Within a first...
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