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Patent # Description
US-9,769,596 Mobile device output to external device
A method for outputting content to an external device comprises receiving with a mobile device, a signal from a first external device, identifying a direction...
US-9,768,304 Method of fabricating a FINFET having a gate structure disposed at least partially at a bend region of the...
A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed...
US-9,768,116 Optimized wires for resistance or electromigration
Optimized metal wires for resistance or electromigration, methods of manufacturing thereof and design methodologies are disclosed. The method includes...
US-9,768,079 Extra gate device for nanosheet
A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is...
US-9,768,028 Semiconductor structure with a dopant implant region having a linearly graded conductivity level and method of...
Disclosed are methods that employ a mask with openings arranged in a pattern of elongated trenches and holes of varying widths to achieve a linearly graded...
US-9,767,240 Temperature-aware integrated circuit design methods and systems
Disclosed are temperature-aware integrated circuit (IC) design methods and systems, which establish a customized power delivery network (PDN) for an IC early in...
US-9,767,239 Timing optimization driven by statistical sensitivites
System and methods for achieving a timing closure in a design of an integrated circuit in presence of manufacturing variation. The method includes running a...
US-9,766,923 Preventing unsafe sharing through confinement of mutable captured variables
The disclosed embodiments provide a system that facilitates the development and execution of a software program. During operation, the system provides a...
US-9,765,978 Low water sensor testing device
A low water sensor testing device having an initial piping unit connected to a hot water boiler and also connected to a first three way purge valve unit, which...
US-9,765,269 System and method for integrated waste storage
The present invention provides integrated bunker storage systems for waste streams based on the composition and characteristics of waste stream. In particular,...
US-9,764,224 Managing challenge events
A method and system for managing a challenge event. At least two participants are selected to participate in the challenge event, in response to receipt of a...
US-9,764,223 Conducting challenge events
A method and system for conducting a challenge event. The challenge event is communicated to at least two participants in a form of an event specification, in...
US-9,763,571 Monitoring a person for indications of a brain injury
Embodiments include methods, systems and computer program products for monitoring a user of a helmet for a traumatic brain injury. Aspects include monitoring...
US-D797,997 Helmet visor
US-9,762,423 High data rate multilevel clock recovery system
Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery...
US-9,762,013 Protective case for portable electronic device with integrated dispensable and retractable charge and sync cable
A protective case for a portable electronic device which incorporates a spool assembly containing a user dispensable and retractable Industry standard or OEM...
US-9,761,712 Vertical transistors with merged active area regions
A method for device layout with vertical transistors includes identifying active area regions in a layout of a semiconductor device with vertical transistors....
US-9,761,526 Interconnect structure having tungsten contact copper wiring
Aspects of the present disclosure include interconnect structures for an integrated circuit (IC) structure and methods of making the same. The interconnect...
US-9,761,525 Multiple back gate transistor
The present disclosure relates to semiconductor structures and, more particularly, to multiple back gate transistor structures and methods of manufacture. The...
US-9,761,482 Enhancement of iso-via reliability
A process of making a semiconductor structure. The process includes forming a wiring line; forming a reliability enhancement material on the wiring line;...
US-9,761,329 Built-in self-test (BIST) circuit and associated BIST method for embedded memories
An integrated circuit chip with a built-in self-test (BIST) circuit having a BIST engine, which is electrically connected to multiple memories, which tests...
US-9,760,673 Application specific integrated circuit (ASIC) test screens and selection of such screens
Various embodiments include approaches for analyzing a customer design for an application specific integrated circuit (ASIC). In some cases, an approach...
US-9,760,665 Validating variation of timing constraint measurements
An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal...
US-9,760,664 Validating variation of timing constraint measurements
An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal...
US-9,760,581 Multiple partial-image compositional searching
Multiple partial-image selections are received. Each of the multiple partial-image selections includes a user-selected portion of one of a group of images....
US-9,760,504 Nonvolatile memory data security
Keys are generated at a memory device with a period of time elapsing between generation of each key. A request is received from a memory controller for the most...
US-9,760,131 276-pin buffered memory card with enhanced memory system interconnect
An embodiment is a memory card including a rectangular printed circuit card having a first side and a second side, a first length of between 151.35 and 161.5...
US-9,760,106 Integrated circuit having regulated voltage island power system
Various embodiments include an integrated circuit (IC) structure having: a chip control logic; a chip power system connected with the chip control logic; and a...
US-9,759,868 Structures for preventing dicing damage
The disclosure relates to semiconductor structures and, more particularly, to structures for preventing dicing damage on photonics wafers. The structure...
US-9,759,767 Pre-test power-optimized bin reassignment following selective voltage binning
Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test...
US-9,759,766 Electromigration test structure for Cu barrier integrity and blech effect evaluations
An electromigration test structure is provided for evaluation of interconnect liner integrity in a semiconductor interconnect structure. The electromigration...
US-9,758,365 Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure
Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, methods of manufacture and design structure are provided. The method...
US-D796,920 Lunch box
US-D796,903 Hydration bladder
US-9,755,863 High data rate multilevel clock recovery system
Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery...
US-9,753,076 Voltage rail monitoring to detect electromigration
An integrated circuit is configured to detect current leakage that results from electromigration in the integrated circuit. An isolation power switch...
US-9,748,271 Hybrid circuit including a tunnel field-effect transistor
The present invention relates generally to integrated circuits and more particularly, to a structure and method of forming a hybrid circuit including a tunnel...
US-9,747,965 Adaptive reference scheme for magnetic memory applications
A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for...
US-9,747,816 Pregnancy education dolls
A set of pregnancy education dolls (1) with an adult female doll (4) resembling a fully developed adult female and a child female doll (5) resembling a young...
US-9,747,773 Suggesting adjustments to a helmet based on analysis of play
Embodiments include method, systems and computer program products for suggesting adjustments to an adjustable helmet based on analysis of play. Aspects include...
US-9,747,552 Using cohorts to infer attributes for an input case in a question answering system
A cohort analysis mechanism analyzes cohorts to infer one or more additional attributes for an input case to provide a refined input case to answer a question...
US-9,747,400 Optimizing placement of circuit resources using a globally accessible placement memory
A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions,...
US-9,747,148 Error monitoring of a memory device containing embedded error correction
Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices...
US-9,746,089 Spool valve assembly with stationary insert
Valve assemblies and associated methods are disclosed that may include a spool valve and one or more stationary inserts. In some examples, the stationary...
US-9,745,787 Movable closure system
Improvements to movable closure systems which aid installability and reliability of said systems can include wheels running along the top and bottom of...
US-9,744,910 Foldable load carrier with a latching brace
A cargo load carrier configured to be mounted at the rear of a carrying vehicle and having a support frame mountable to the vehicle. A load carrying member is...
US-D795,990 Fishing lure
US-D795,853 Router
US-9,741,722 Dummy gate structure for electrical isolation of a fin DRAM
Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the...
US-9,741,707 Immunity to inline charging damage in circuit designs
Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor...
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