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Patent # Description
US-9,900,147 Homomorphic encryption with optimized homomorphic operations
The techniques and/or systems described herein are directed to improvements in homomorphic operations within a homomorphic encryption scheme. The homomorphic...
US-9,896,475 Pyridyl analogs of 1-(2-cyano-3,12-dioxooleana-1,9(11)dien-28-oyl) imidazole
Pyridyl analogs of 1-(2-cyano-3,12-dioxooleana-1,9(11)-dien-28-oyl) imidazole and pharmaceutical compositions containing the same are provided. The present...
US-9,895,829 Post-mold system
Disclosed herein, amongst other things, is a post-mold system (100, 200, 300, 400, 500) for conditioning a molded article (130). The post-mold system comprises...
US-9,893,948 Network management using hierarchical and multi-scenario graphs
A method, system, and computer program product to manage a network comprising a plurality of interconnected components are described. The method includes...
US-9,893,811 Architecture for a wireless network
A ferrule for a fiber optic connector includes: a main body extending from a first end to a second end, the main body defining a bore extending from the first...
US-9,893,765 Transmission system having duplicate transmission systems for individualized precharge and output timing
Devices include a primary transmission system, and first and second duplicate (dummy or non-transmitting) transmission systems. The primary transmission system...
US-9,893,157 Structures with contact trenches and isolation trenches
Structures that include contact trenches and isolation trenches, as well as methods for forming structures including contact trenches and isolation trenches. A...
US-9,893,023 Semiconductor chip with anti-reverse engineering function
A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first...
US-9,892,999 Producing wafer level packaging using leadframe strip and related device
A method for producing wafer level packaging using an embedded leadframe strip and the resulting device are provided. Embodiments include placing dies into a...
US-9,892,970 Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same
One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: providing a substrate having a front side...
US-9,892,958 Contact module for optimizing emitter and contact resistance
An advanced contact module for optimizing emitter and contact resistance and methods of manufacture are disclosed. The method includes forming a first contact...
US-9,892,321 Using maximal inscribed spheres for image-based rock property estimation
A method for analyzing a rock sample comprises analyzing a three dimensional image of the rock sample using maximal inscribed sphere analysis to determine...
US-9,892,095 Reconciliation of transcripts
The method includes identifying a plurality of transcripts of an audio event. The method further identifying a difference between two or more of the plurality...
US-9,891,275 Integrated circuit chip reliability qualification using a sample-specific expected fail rate
Disclosed is a method for performing reliability qualification of manufactured integrated circuit (IC) chips. In the method, IC chips are manufactured according...
US-9,891,261 Electromigration monitor
A structure, such as a wafer, chip, IC, design structure, etc., includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV extends...
US-9,889,517 Method for selection of weld control algorithms
A system and method for generating a weld are provided. The system receives a selection of a magnitude of a voltage. The system selects a first weld control...
US-D809,899 Illuminated light switch plate
US-9,888,098 Orchestrating resources in a multilayer computing environment by sending an orchestration message between layers
Software that generates a message containing program instructions for multiple layers in a multi-layer environment, by performing the following operations: (i)...
US-9,887,193 Integrating a planar field effect transistor (FET) with a vertical FET
One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a...
US-9,887,192 Interconnects for vertical-transport field-effect transistors
Structures and fabrication methods for vertical-transport field-effect transistors. The structure includes a vertical-transport field-effect transistor having a...
US-9,887,156 Backside device contact
A back-side device structure with a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, a trench that extends through the...
US-9,886,998 Self pre-charging memory circuits
The present disclosure relates to semiconductor structures and, more particularly, to sensing circuit for a memory and methods of use. The memory includes a...
US-9,886,993 Protocol for memory power-mode control
In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store...
US-9,886,541 Process for improving capacitance extraction performance
Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout...
US-9,886,505 Interacting with phone numbers and other contact information contained in browser content
The present invention discloses a method for handling contact information in a communication device. The method can include a step of presenting content within...
US-9,886,423 Reconciliation of transcripts
The method includes identifying a plurality of transcripts of an audio event. The method further identifying a difference between two or more of the plurality...
US-9,886,389 Cache memory bypass in a multi-core processor (MCP)
This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A...
US-9,883,612 Heat sink attachment on existing heat sinks
Structures and methods for providing heat sink attachments on existing heat sinks. According to a device, a first heat sink comprises a first base and fins...
US-9,882,782 Network management using hierarchical and multi-scenario graphs
A method, system, and computer program product to manage a network comprising a plurality of interconnected components are described. The method includes...
US-9,882,414 Tetherless device charging for chained devices
In one embodiment, a method includes integrating a charging pad into a powered device having a power supply, where the powered device is at least one of a...
US-9,882,377 Electrostatic discharge protection solutions
Electrostatic discharge protection circuits and methods for protecting a core circuit from an electrostatic discharge event. The protection circuit may include...
US-9,882,376 Electrostatic discharge power clamp with fail-safe design
Electrostatic discharge protection circuits and methods of fabricating an electrostatic discharge protection circuit, as well as methods of protecting an...
US-9,882,081 Photodetector methods and photodetector structures
Disclosed are a method of forming a photodetector and a photodetector structure. In the method, a polycrystalline or amorphous light-absorbing layer is formed...
US-9,882,048 Gate cut on a vertical field effect transistor with a defined-width inorganic mask
A method of cutting a gate on a VFET includes depositing a memorization layer around a spacer on a sidewall of the field effect transistor. A planarizing layer...
US-9,882,021 Planar III-V field effect transistor (FET) on dielectric layer
A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in...
US-9,881,956 Heterogeneous integration using wafer-to-wafer stacking with die size adjustment
A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer....
US-9,881,925 Mirror contact capacitor
A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a bonding layer in contact with a top...
US-9,881,810 Structures, methods and applications for electrical pulse anneal processes
Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure...
US-9,881,694 Built-in-self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing...
US-9,881,666 Overvoltage protection for a fine grained negative wordline scheme
A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including...
US-9,881,323 Providing hard-to-block advertisements for display on a webpage
Methods and systems of the invention provide advertisements or other content for a webpage. An example is providing portions of an advertisement as separate...
US-9,879,195 Systems and methods for processing a heterogeneous waste stream
Systems and methods for processing and sorting a municipal solid waste stream are described herein. A system can include a processing sub-system configured to...
US-9,875,945 Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor
An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal...
US-9,875,917 Semiconductor bonding apparatus and related techniques
A semiconductor structure bonding apparatus is disclosed. The apparatus may include a leveling adjustment system configured to provide leveling adjustment of...
US-9,875,780 STT MRAM source line configuration
Improved STT MRAM source line configurations are provided. In one aspect, a STT MRAM array includes: a plurality of cells including magnetic tunnel junctions in...
US-9,873,855 Cleaning formulations and uses thereof
Cleaning compositions and methods of using such compositions. The compositions comprise oxidizing agent(s); weak acid(s), and surfactant(s) (e.g., a combination...
US-9,871,523 High speed level translator
A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a...
US-9,871,020 Through silicon via sharing in a 3D integrated circuit
The present disclosure generally relates to semiconductor structures and, more particularly, to intelligent through silicon via sharing in 3D-IC integrated...
US-9,870,979 Double-sided segmented line architecture in 3D integration
Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided...
US-9,870,851 Low temperature fabrication of lateral thin film varistor
A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do...
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