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Patent # Description
US-9,577,850 Control actuation smoothing
The present disclosure relates to control actuation smoothing, and more particularly, to a control actuation smoothing system that smoothes brake actuation. The...
US-9,577,596 System and method for personalization of an audio equalizer
The invention is directed to synthesizing a personalized audio equalization filter based on an individual's hearing profile when listening to audio signals...
US-9,577,461 Multi axis vibration unit in device for vectored motion
Charging a first device by a second device. The first device determines a first position of the first device relative to the second device. Based on the...
US-9,577,038 Structure and method to minimize junction capacitance in nano sheets
A method of making a semiconductor device includes forming a nanosheet stack including a first layer and a second layer; patterning a gate stack on the...
US-9,577,023 Metal wires of a stacked inductor
A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical...
US-9,576,899 Electrical fuse with high off resistance
Electrical fuses and methods for forming an electrical fuse. A semiconductor substrate is implanted to define a modified region in the semiconductor substrate....
US-9,576,880 Dual damascene structure with liner
A dual damascene structure with an embedded liner and methods of manufacture are disclosed. The method includes forming a dual damascene structure in a...
US-9,576,863 Method of fine-tuning process controls during integrated circuit chip manufacturing based on substrate backside...
Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are...
US-9,576,682 Traffic and temperature based memory testing
The method may include accessing, with a first stress test, a plurality of memory modules, the plurality of memory modules coupled in a computer system, the...
US-9,575,904 Memory data security
A memory module secures data stored on the memory module. A request for the data from a computer system is received by the memory module. A verification key...
US-9,575,728 Random number generation security
A technique for improving random number generation (RNG) security for a data processing system includes a storage subsystem of a processing unit receiving a...
US-9,575,115 Methodology of grading reliability and performance of chips across wafer
A system and method sorts integrated circuit devices. Integrated circuit devices are manufactured on a wafer according to an integrated circuit design using...
US-9,574,864 Gauge for installation of liners in substrate spin coating tools
A gauge and method of use. The gauge includes a body configured to removeably mount to substrate chuck of a spin apply coating tool, the body rotatable about an...
US-9,574,653 Ring gear stabilization for powerglide transmissions
Systems and methods for stabilizing the ring gear in a Powerglide transmission are disclosed. Systems may include a radial stabilization member mountable to the...
US-9,574,551 Power tower--system and method of using air flow generated by geothermal generated heat to drive turbines...
Apparatus is provided having one or more SWEGS that may be configured to heat air in a draft power tower arrangement. In a closed loop, cold fluid may be pumped...
US-9,573,429 Carrier insert bar assembly with securement pin
An insert bar assembly for a hitch-rack carrier comprises a self-locating securement pin. The insert bar assembly can comprise an elongate hitch-attachment bar...
US-9,571,263 Integrated circuit incorporating a low power data retiming circuit
A low power data retiming circuit incorporates CMOS components in certain sections that operate at a lower frequency in comparison to certain other sections...
US-9,570,564 Self-aligned emitter-base bipolar junction transistor with reduced base resistance and base-collector capacitance
Device structures and fabrication methods for a bipolar junction transistor. A first semiconductor layer is formed on a substrate containing a first terminal....
US-9,570,538 Methods of manufacturing polyresistors with selected TCR
Various embodiments provide computer program products and computer implemented methods. In some embodiments, aspects provide for a method of manufacturing a...
US-9,570,422 Semiconductor TSV device package for circuit board connection
An electronic device includes a circuit board and a semiconductor device package. The semiconductor device package includes a laminate layer. The semiconductor...
US-9,570,389 Interconnect structure
An interconnect structure includes a dielectric layer with one or more trenches extending therein, one or more interconnect lines, and one or more first liner...
US-9,570,363 Vertically integrated memory cell
A method of forming a vertically integrated memory cell including a deep trench extending into a substrate, a trench capacitor located within the deep trench,...
US-9,570,357 Vertical field effect transistors
Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure...
US-9,570,199 Traffic and temperature based memory testing
The method may include accessing, with a first stress test, a plurality of memory modules, the plurality of memory modules coupled in a computer system, the...
US-9,570,156 Data aware write scheme for SRAM
Approaches for providing write-assist for a Static Random Access Memory (SRAM) array are provided. A circuit includes a control circuit connected to a cell in a...
US-9,570,155 Circuit to improve SRAM stability
Approaches for stability of cells in a Static Random Access Memory (SRAM) array are provided. A circuit includes a precharging circuit configured to precharge...
US-9,569,571 Method and system for timing violations in a circuit
A method for controlling a circuit, the method comprises performing a first timing analysis of an digital integrated design, identifying a critical path in the...
US-9,569,109 Nonvolatile memory interface for metadata shadowing
A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in...
US-9,568,538 Matching of bipolar transistor pair through electrical stress
A method for matching a pair of matched bipolar transistors in an integrated circuit is disclosed. Within a device, it is determined which transistor is a...
US-9,568,487 Oxidized LDL as a biomarker for neurological complications of pregnancy
Methods for diagnosing and treating conditions associated with life-threatening neurological complications are provided. The methods involve in some aspects the...
US-9,567,942 Centrifugal turbomachines having extended performance ranges
Centrifugal turbomachines, such a centrifugal compressors, centrifugal blower, and centrifugal pumps, having unique treatments that enhance their performance...
US-9,566,562 High-temperature open-cell porous ceramic
A high-temperature open-cell porous body, the body comprises crystalline inorganic particles and 0.5 to 3-weight percent glass. The crystalline inorganic...
US-9,564,508 Device isolation with improved thermal conductivity
A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a...
US-9,564,445 Dummy gate structure for electrical isolation of a fin DRAM
Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the...
US-9,564,443 Dynamic random access memory cell with self-aligned strap
After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall...
US-9,564,184 Sense amplifier for single-ended sensing
A single ended line sense amplifier having an input coupled to a single ended line having a near end and a far end device comprises a plurality of nFET stacks...
US-9,564,183 Sense amplifier having a timing circuit for a presearch and a main search
A line sense amplifier comprises: a presearch block, a main search block, and a timing circuit. The presearch block is coupled to a presearch line for sensing...
US-9,564,180 Deep-sleep wake up for a memory device
A memory device comprises memory banks, power gates, and bank wake-up circuits. Each of the memory banks has a core voltage supply. The power gates are coupled...
US-9,562,573 Replacement forward drum and method in certain automatic transmissions
Systems, devices, and methods for a replacement forward drum for Ford's 4R70E/W and 4R75E/W transmissions. In one embodiment, a replacement forward drum is...
US-9,561,505 Sample preparation devices and systems
Devices and system for preparing samples are described. Such devices can comprise fluidic chambers, reservoirs, and movable structures for controlling the...
US-RE46,303 Isolation region fabrication for replacement gate processing
A method for isolation region fabrication for replacement gate integrated circuit (IC) processing includes forming a plurality of dummy gates on a substrate;...
US-9,559,162 Thermoresistance sensor structure for integrated circuits and method of making
A first pair of resistors formed in a first layer of material, and a second pair of resistors formed in the first layer or in a second layer can be wired into a...
US-9,559,040 Double-sided segmented line architecture in 3D integration
Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided...
US-9,558,850 Efficient calibration of a data eye for memory devices
A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration...
US-9,558,187 Enhanced document input parsing
An approach is provided for an information handling system that includes a processor and a memory to analyze documents. In the approach, an electronic document...
US-9,558,018 Methods and apparatus for simulating a distributed business process
Methods and apparatus for simulating a distributed business process are disclosed. The methods and apparatus simulate an interdependent business process, such...
US-9,557,974 System and method for supporting compatibility checking for lambda expression
A system and method can support compatibility checking in a programming language environment. The programming language environment can check whether a target...
US-9,557,505 Power and optical fiber interface
A power and optical fiber interface system includes a housing having an interior. A cable inlet is configured to receive a hybrid cable having an electrical...
US-9,557,381 Physically aware insertion of diagnostic circuit elements
According to an embodiment of the present invention, a computer-implemented method for inserting diagnostic circuit elements in a scan chain of a chip may...
US-9,557,378 Method and structure for multi-core chip product test and selective voltage binning disposition
Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into...
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